1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device which uses a ferroelectric capacitor as a memory element at the time of read-out operation.
2. Description of the Related Art
In a nonvolatile semiconductor memory device, such as a flash memory, a reference current, read from a reference cell therein, is set to a predetermined threshold level (or a fixed reference level), and at the time of read-out operation, a drain current from a memory cell accessed therein is read out as the data, and the read-out current of the memory cell is compared with the reference current of the reference cell. The determination as to whether the data is “1” or “0” is performed depending on whether the read-out current is higher than the reference current or not.
When the number of times of rewriting the memory cell in the nonvolatile semiconductor memory device increases, the charge loss in which the writing charge is lacked will occur, and it is in the tendency for the threshold level of the memory cell in the core memory area to become small. On the other hand, the rewriting operation is not normally performed to the reference cells in the reference cell area, and the fixed reference voltage from the reference cells will remain unchanged. For this reason, when the number of times of rewriting increases, the read-out operation is not properly executed with the fixed threshold voltage of the reference cell, and only an inadequate read-out margin is left for the read-out operation.
There is a reference cell setting technique that is used to secure an adequate read-out margin. In this technique, the two reference cells with respect to the data “1” and “0” are provided in the memory cell array as the reference cells for read-out operation. The average of the reference current values from the two reference cells is obtained. The rewriting operation is performed to the reference cells, similar to the memory cells in the core cell area of the memory cell array. Namely, the reference cell REF-0 and the reference cell REF-1 are respectively provided for the data “0” which corresponds to the cell in the programmed state and the data “1” which corresponds to the cell in the erased state. The average of the reference current values from the two reference cells is obtained by reading the drain current from each of the reference cells REF-0 and REF-1, and it is used as the reference level for the data discrimination.
In the case of the above-described technique, the REF-0 is programmed like the memory cell using the reference cell PrRef for program verification check that is set to a predetermined threshold level. In the program verification check, the reference current from the reference cell PrRef for program verification and the read-out current from the memory cell being written thereto are compared. When the read-out current from the memory cell reaches the threshold level that is higher than the reference current, the rewriting operation is ended.
Therefore, only the lower limit is set up for the threshold level of the reference cell REF-0 programmed in the above manner, and it is uncertain whether the actually set threshold level is appropriate. Similarly, only the upper limit is set up for the threshold level of the reference cell REF-1 programmed in the above manner, and it is uncertain whether the actually set threshold level is appropriate.
Hence, the threshold level of the reference cell has the probability distribution with the spread of the amplitude depending on the writing/erasing characteristics. The distribution of the threshold level of the virtual read-out reference cell which is the average of the reference current values from the two reference cells has significant influence on the read-out margin.
When the threshold level of the virtual read-out reference cell is relatively high, the threshold difference with the data “0” of the memory cell becomes small, and the read-out margin on the side of “0” becomes small.
When the threshold level of the virtual read-out reference cell is relatively low, the threshold difference with the data “1” of the memory cell becomes small, and the read-out margin on the side of “1” becomes small.
Accordingly, variations exist in the threshold level of each reference cell depending on the characteristics of the writing and erasing of the reference cell when the average of the reference currents of the two reference cells is obtained as the reference level, variation will arise also on the reference current which is the average of the reference currents of the two reference cells, and the read-out margin will become unstable.
Meanwhile, a nonvolatile semiconductor memory device such as an ordinary flash memory has the configuration in which a plurality of memory cells are arranged in row and columns each memory cell using polysilicon etc. as the floating gate.
On the other hand, a flash memory which is configured by using the two-bit-per-cell technology has been developed and it is going to be put in practical use. In such memory device, 2 bits of information are stored in the memory cell by trapping the charge in a layer of a silicon nitride film or the like. Hereinafter, each memory cell of such flash memory is called a double bit cell.
Japanese Laid-Open Patent Application No. 2001-156272 discloses a non-volatile semiconductor memory device (flash memory) which implements the two-bit-per-cell technology using a charge-trap layer.
FIG. 1 shows the structure of a double bit cell.
In the flash memory of this type, for example, a charge-trap layer is provided between the control gate and the substrate for each memory cell, and the trap layer is comprised of a silicon oxide film, a silicon nitride film and a silicon oxide film which are stacked together in this order. Two bits of information, or the data “1” and the data “0”, are stored in the memory cell by trapping the charge in the layer of the silicon nitride film. The threshold level of the memory cell is varied depending on whether the charge is trapped or not, and the readout current is distinguished between the data “0” and the data “1”. In this case, the trap layer, such as silicon nitride, is an insulating film, and the charge is not transferred from the trap layer. Therefore, storing two bits of information per cell is possible by trapping the charge at the ends of the trap layer independently. The two bits of information can be separately read by changing the drain and the source of the cell transistor at the time of read-out operation respectively.
In the flash memory of the above type, when performing a program verification operation of the target memory cell, the leak current will occur in the neighboring memory cell that is adjacent to the target memory cell and connected to the common word line. In the program verification mode, as the program verification current flows to the target memory cell, a voltage is applied to the common word line for the target memory cell and its neighboring memory cell. Hence, the leak current will occur in the neighboring memory cell due to the applied voltage.
If the leak current occurs, it is difficult to correctly detect the exact magnitude of the program verification current of the target memory cell.
FIG. 2 is a diagram for explaining the leak current generated in the neighboring memory cell adjacent to the target memory cell in a conventional nonvolatile semiconductor memory device.
Suppose that the memory cell array of the nonvolatile semiconductor memory device of FIG. 2 is arranged so that a plurality of memory cells, such as memory cells 61, 62, 63 and 64, are connected to the common word line.
Each memory cell has the same configuration as the memory cell of FIG. 1, and the nonvolatile semiconductor memory device of FIG. 2 is configured by using the two-bit-per-cell technology described above.
For the sake of convenience of description, the case in which the bit line A side of the memory cell 61 of FIG. 2 is made into the program verification state is considered. On the other hand, however, it is possible to consider the case in which the bit line B side of the memory cell 61 of FIG. 2 is made into the program verification state in the same way as described below.
In the example of FIG. 2, after the application of a program pulse, the bit line A side of the memory cell 61 is made into the program verification state. The verification current will flow, in the direction of the arrow indicated in FIG. 2, to the bit line A side of the target memory cell 61.
Suppose that the bit line A of the target memory cell 61 is set to a ground voltage (Vss).
When the magnitude of the verification current is smaller than the predetermined reference current, the data stored in the bit line A side of the target memory cell 61 is correctly read out by the sense amplifier 32.
At this time, when the bit lines C and D of the neighboring memory cell 62, the bit lines E and F of the neighboring memory cell 63, and the bit lines G and H of the neighboring memory cell 64 are set in the erased state, the leak current flows, in the direction of the arrow indicated in FIG. 2 that is opposite to the direction of the verification current, to the neighboring memory cell 62 and others connected to the common word line, because the word line of the target memory cell 61 is activated.
Therefore, it is difficult to read correctly the exact magnitude of the verification current of the target memory cell 61 with the sense amplifier 32 because of the influence of the leak current generated in the neighboring memory cell 62.
The influence of the leak current of the neighboring memory cell 62 is given to the conventional nonvolatile semiconductor memory device without compensation, and the determination result of data is not reliable at the time of the comparison of the read-out current and the reference current.